1. Field of the Invention
The present invention is directed in general to data communications. In one aspect, the present invention relates to a method and system for improving memory read and write operations in microprocessor or multiprocessor computer devices.
2. Related Art
As is known, communication technologies that link electronic devices may use computer system switching devices to route and process signal information. Some communication technologies interface one or more processor devices for processing packet-based signals in a network of computer systems, and typically include one or more receive/transmit interfaces. These interfaces generally function to convert data from a high-speed communication protocol (e.g., HT, SPI, etc.) utilized between processor devices and the generic format of data utilized within the processor device. The generic format may include 8 byte data words or 16 byte data words formatted in accordance with a proprietary protocol, in accordance with asynchronous transfer mode (ATM) cells, in accordance with internet protocol (IP) packets, in accordance with transmission control protocol/internet protocol (TCP/IP) packets, and/or in general, in accordance with any packet-switched protocol or circuit-switched protocol.
Each interface typically includes a dedicated DMA engine used to transmit received packets from the receive interface to memory in the system over a system or memory bus, and to transmit packets from the memory over the memory bus to the transmit interface for transmission. If a given system includes two or more packet interfaces, the system includes DMA engines for each interface. Such conventional systems typically include an I/O bus (for example, in the receive interface) that has the same width as the memory bus, making for straightforward transfers between the busses. But where the data to be written to or read from memory does not match or align with the memory block size (such as occurs when descriptors are used to point to multiple cache buffers storing a data packet), the DMA engine in such conventional systems must perform a Read-Modify-Write (RMW) operation in order to write the data back to the memory. This requires the DMA engine to wait for reads from the main memory for each RMW operation, thereby degrading the speed and performance of the DMA engine. For data read operations, data from memory must be converted to fit the bus width requirements of the transmit interface. When multiple channels are executing DMA transfers, an additional challenge is posed by having to maintain partial results for all active channels.
Therefore, a need exists for methods and/or apparatuses for improving the processing of memory transfers to quickly and efficiently transfer data to and from memory. Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.